As the name tells us, the capacitors consist of ceramic. The manufacturing process starts with a finely grounded ceramic powder mixed with an emulsion of solvents and resin binders. In the first manufacturing step, the emulsion is dried to a soft film and screen printed with an electrode paste; historically, it was a compound of palladium or silver and palladium + binding agents. Due to the high cost of palladium, this termination style was replaced by metals like copper and nickel, so-called base metal electrodes (BME) that is a majority of today’s MLCC designs.
So-called tube capacitors are extruded out of a nozzle. They are covered with an electrode paste on the inside and the outside before it’s sintered to their definite material structure. In the same way, the Single Layer Ceramic Capacitor (SLCC or just SLC) consists of one dielectric layer. The ceramic is covered with an adhesive layer of, for example, chrome nickel as a base for copper electrodes. On the electrodes, leads are soldered, as shown in Figure 5., before the component is encapsulated in lacquer or epoxy.
This article is the second part of a complete installment on the construction, manufacture, application and characteristics of ceramic capacitors, divided into 4 sections:
- Introduction to Ceramic Capacitors
- Construction & Manufacturing Process
- Ceramic Capacitors Class 1
- Ceramic Capacitors Class 2
Figure 4. SLCC ceramic capacitors view; source: Vishay
Figure 5. Principle sketch of a single layer ceramic capacitor
The most common ceramic capacitor design is the multi-layer construction where the capacitor elements are stacked, so-called MLCC (Multi-Layer Ceramic Capacitor). The number of layers has to be limited for the manufacturing technique. The upper limit amounts at present to over 1000. Besides, economic reasons come into play. On larger case sizes, stacking operation becomes less productive and raises the price steeply at higher capacitance values. The lowest capacitance values are achieved by only two layers, often separated by double ceramic layers.
MLCC Manufacturing Process
In the conventional dry method, the ceramic emulsion is dried on a conveyor belt before being separated from the supporting bed. Then, it is cut into “primary sheets” that are screen printed with electrode paste for a large number of chips. These primary sheets are then stacked in an accurate steel frame and pressed to a solid piece to make it possible to cut out the separate chips from the stack with the electrodes in alternating positions.
In the latest variant of this method, a conveyor film is utilized for the ceramic emulsion, reducing the dielectric thickness to 3 μm (0.1 mils). Here, quality implies manufacturing in extremely “clean rooms,” i.e., rooms with filtered air and control of the number and size of particles.
The so-called wet method became increasingly common before the variant with a conveyor film was used in the dry method. The stage with the handling of “primary sheets” is skipped by letting the emulsion dry in “primary sheet frames.” In combination with better milling methods for the ceramic powder and a higher material purity, the wet method makes it possible with thinner dielectrics without a growing failure rate.
MLCC consists of several individual capacitors stacked parallel and contacted via the terminal surfaces. The starting material for all MLCC chips is a mixture of finely ground granules of raw materials modified by accurately determining additives. These powdered materials are mixed homogeneously. The mixture’s composition and the powder particles’ size, as small as 10 nm, reflect the manufacturer’s expertise.
Figure 6. MLCC ceramic capacitor manufacturing process; source: Wikipedia
A thin ceramic foil is cast from a powder suspension with a suitable binder. This foil is rolled up for transport. Unrolled again, it is cut into equal-sized sheets and screen-printed with a metal paste. These sheets become the electrodes. In an automated process, these sheets are stacked in the required number of layers and solidified by pressure. Besides the relative permittivity, the size and number of layers determine the later capacitance value. The electrodes are stacked in an alternating arrangement slightly offset from the adjoining layers so that they can later be connected on the offset side; one left, one right. The layered stack is pressed and then cut into individual components. For example, high mechanical precision is required to produce a 500 or more layer stack of size “0201” (0.5 mm × 0.3 mm).
After cutting, the binder is burnt out of the stack. This is followed by sintering at temperatures between 1,200 and 1,450 °C, producing the final, mainly crystalline, structure. This burning process creates the desired dielectric properties. Burning is followed by cleaning and then metallization of both end surfaces. The ends and the inner electrodes are connected in parallel through metallization, and the capacitor gets its terminals. Finally, a 100% measuring of the electrical values will be done, and the taping for automated processing in a manufacturing device will be performed.
There are two basic termination structures – BME Base Metal Electrodes based on copper and nickel metals and PME Precious Metal Electrodes based on silver palladium metals. The original technologies mostly used PME structure, but palladium’s high prices pushed the industry to seek alternatives. The advantage of PME has been its TCE compatibility with the glass dielectric and, thus, lower stress during the firing process. However, BME is now the dominating structure and is subjected to the latest development. Thus, higher CV capacitors are available in BME configuration, while PME is used in mission-critical applications such as space or defence.
Figure 7. MLCC stacked MLCC capacitor construction
Figure 8. BME termination MLCC structure; source: TDK
Figure 9. PME (AgPd) termination MLCC structure; source: TDK
The separate cut loose chips are subjected to a first heat treatment (burn-out), during which the organic binding agents—as part of the electrode paste—are gasified and diffused through the not-yet sintered ceramic. If this process is forced too fast, bubbles form that will separate electrodes and ceramics and result in so-called delaminations (Figure 10).
The dielectric thickness, the number of electrode layers, and the active capacitive area determine the capacitance in certain chip sizes. The thickness is varied by using one or several layers. However, the risk of short-circuit failures increases when we are on the way towards higher capacitances, passing from two to one layer. It will be at maximum when we pack the chip with the maximum number of layers. At the same time, the risk of delamination increases. A practical limit where it may be advisable to avoid this twofold risk range by a size exchange is approximately 20% below the usual start overlapping in the next chip size (Figure 11).
We can also buy “high-rel” components, for example, according to MIL-C-123, which specifies limits for the delamination extent and states methods for X-ray diagnosis. The price, however, will be approximately 20 times higher than that of a conventional standard component, and the success of the X-ray check is debatable. Other ultrasonic methods are developed, but the result is often difficult to interpret. Besides, such equipment is expensive. In conclusion, only “space” and other “high rel” applications motivate the price we must pay for the increase in quality.
The burn-out process shouldn’t be forced too fast because of provoked delamination. On the other hand, it may not last too long. Then much of the palladium content of the electrode paste will oxidize. In other words, the time-temperature profile must be kept at an optimum level for the ceramic and electrode material.
Figure 10. Schematic of an MLCC ceramic capacitor delamination
Figure 11. Rule of thumb for changing chip size.
After the burn-out process follows the considerably faster sintering of ceramic and electrode materials. Also, a check off the time-temperature profile is extremely vital, not least the cooling time if we shall avoid micro-cracks in the ceramic.
After the sintering terminations are applied, which consist of…
The risk of delamination also increases with the number of layers. Primarily it depends on the quantity of electrode metal in the ceramic and the differences in TCE (coefficient of expansion) of these materials. At the maximum capacitance in certain chip sizes, delamination is nearly unavoidable.
Now, delamination may not be as catastrophic as we fear. If the capacitor is not subjected to extreme humidity that might diffuse into the cavities and the soldering is executed without any unsymmetrical heat conduction that may cause cracks in the ceramic, we will never become aware of any delaminations (unless we deal with high voltage capacitors where the corona effect may be dangerous). The author believes only soldering with a soldering iron will cause such temperature gradients that the ceramic may crack. However, there are other reasons why avoiding the highest capacitance values may be advisable.
If the component operates at high electric field strengths or in severe mechanical acceleration or chock environments, we should, in any case, avoid maximum capacitance values in that size class, i.e. reduce the capacitance or increase the mechanical size.
We can also buy “high-rel” components, for example, according to MIL-C-123, which specifies limits for the delamination extent and states methods for X-ray diagnosis. The price, however, will be approximately 20 times higher than that of a conventional standard component, and the success of the X-ray check is debatable. Other ultrasonic methods are developed, but the result is often difficult to interpret. Besides, such equipment is expensive. In conclusion, only “space” and other “high rel” applications motivate the price we must pay for the increase in quality.
The burn-out process shouldn’t be forced too fast because of provoked delamination. On the other hand, it may not last too long. Then, much of the palladium content of the electrode paste will oxidize. In other words, the time-temperature profile must be kept at an optimum level for the ceramic and electrode material.
After the burn-out process, ceramic and electrode materials are considerably faster sintered. Also, checking the time-temperature profile is vital, not least the cooling time, if we are to avoid micro-cracks in the ceramic.
After the sintering terminations are applied, which consist of…
- farthest BME or Ag/Pd in good adhesion to the ceramic, 15…40 μm (0.6…1.6 miles)
- possibly a barrier layer (Ni) that will prevent silver from dissolving into the solder, 1…3 μm (0.04…0.1 mils) and
- farthest out Sn, 3…10 μm (0.1…0.4 mils) or solder, 10…100 μm (0.4…4 miles)
If the inner electrodes consist of nickel or copper, compatible termination materials must be utilized. For that reason, nickel or copper-based compounds are developed for outer terminations. They have a low migration and must only be covered with a solderable alloy.
Figure 12. The spherical shape of a hot tinned layer
High Voltage SMT Ceramic Capacitors
Surface mount high voltage multilayer ceramic capacitors (HV MLCCs) appear to be pretty much identical to standard configuration MLCCs. They have the same basic form, fit, and function, but several key differences exist.
Typically, as a matter of definition, high voltage MLCCs have rated voltages that are greater than or equal to 200VDC. High voltage MLCCs are typically available in EIA sizes from 0603 to 2225 or larger (metric 1608 to 5664) with voltage ratings from 200V to 5,000V or more. Smaller case high voltage MLCCs typically have lower maximum rated voltages (VRated) as the external terminals tend to be closer than larger case high voltage MLCCs.
High voltage MLCCs are generally available with Class 1 (C0G) or Class 2 (e.g., Ferroelectric X7R) ceramic dielectrics with tolerances that are as good as +/-5% or better as wide as +/-20% or higher. Because of the generally thicker dielectric thicknesses used in the design and potentially the “cascade” or “floating electrode” type designs, the maximum capacitance values available are significantly lower than standard MLCCs.
HVMLCCs appear similar to standard configuration MLCCs. It seems that it should be straightforward to design an HVMLCC of a given voltage rating; just keep increasing the dielectric thickness (DT) to enable the voltage rating desired, as you would with a standard configuration MLCC. The increase in DT is typically about 200 to 250 Volts per thousandth of an inch (V/mil, or ~7.8 to 10 V/μm).
There is a penalty in capacitance per unit volume (C/V) using this approach to increasing rated voltage, as it requires increasing DT. The penalty in C/V is proportional to DT-2 following the relationship:
Standard MLCCs have no crack protection and are normally used for non-critical applications.
Soft termination (Flexiterm, Flexcrack, etc…, trade names) is based on the principle of introducing a soft, conductive layer (usually conductive polymer) to the MLCC terminals that absorb mechanical stress. See the figure on the right.
These capacitors can withstand up to 2-5mm of board flexure without internal cracks. Beyond 5mm, capacitors will generally fail “open,” Thus, this style is the preferred solution today for automotive and higher reliability applications.
Figure 13. MLCC ceramic capacitor soft termination (orange layer)
Electro-plating of tin as the outermost layer also gives an evenly thick layer on edges and corners. However, because of a perpendicular orientation of the tin crystals against the surface, they leave access to oxidizing oxygen if the tin layer is too thin. Therefore, it should be 10 then 3 μm thick (0.4 mils rather than 0.1 mils). Hot or dip tinning creates a very tight layer but is unevenly thick. The covering on the corners becomes thin.
Flexible soft termination
Fail-Safe Multilayer Ceramic Capacitors (MLCCs)
Multilayer ceramic capacitors are highly susceptible to mechanical cracking due to their brittle nature. It is necessary for circuit board manufacturers to ensure that their board handling techniques do not expose boards to excessive bending (board flex) during manufacturing and operation. Some of the processes that can expose boards to excessive bending include mounting in assembling and depanelization. Unsupported input/output edge connectors and pick-and-place equipment can also cause excessive bending.
Figure 14. Approximate normalized capacitance vs. dielectric thickness (linear (left) and log-log (right)); source: Venkel
The above penalty in C/V as the voltage rating is increased is not the only factor to consider; however, the above assumes that a constant rate of increase in DT is appropriate to achieve an increased voltage rating. While this is true, typically to ~1,000 to ~1,500VRated ceramic dielectrics tend to deviate from that rate as VRated is increased above ~1,000 to ~1,500V, resulting in a different VRated vs. dielectric thickness relationship of the lower slope. A hypothetical example of this is given in the Figure below.
We can use floated electrodes (FE) or cascade electrode MLCCs to increase VRated with a relatively minimized impact on C/V as compared to standard configuration MLCCs at lower voltages (i.e., <~1,000V to ~1,500V). As each FE has an additional margin area associated with it, the impact of additional margins on C/V in small case MLCCs (typically EIA 0603 and 0805) may be prohibitive. Still, for larger MLCCs (e.g., EIA 1206 to 2225) the impact is acceptable to relatively small.
Figure 15. Dielectric thickness vs. rated voltage for a typical ceramic dielectric used in MLCCs; source: Venkel
As in Figure 16. below, C/V decreases commensurately with (1/2n2), where n is the number of FEs within the design. VRated also increases with 2n, as does ESR. The effect on ESR is largely compensated for, however, as the two or more internal capacitors typically have more electrodes in each internal capacitor stack (N), thereby reducing ESR within each capacitor in series, and since the aspect ratio of said electrodes within each of the internal capacitors in series has relatively wide and short electrodes, which results in further decreased ESR. These two factors work together to reduce ESR such that the projected ESR increase is typically negligible and may even be reduced compared to standard configuration MLCCs of similar VRated.
Other Construction Types
RF Thin Film Ceramic Capacitors
Thin-film ceramic capacitors use a single-layer low-loss ceramic dielectric packaged as a multilayer ceramic capacitor (MLCC) – see figure below. Its advantage is in very tight capacitance tolerance (even low batch-to-batch variation) and a single resonant point response. Thus such designs are ideal for RF and microwave filter designs.
Figure 17. thin film ceramic capacitor construction
A thin-film capacitor has an extremely repeatable frequency response compared to MLCCs. However, it is also important to realize the limitations of thin-film capacitors used as band-reject filters. Since thin-film capacitors are typically only available in low capacitance values, they are limited to relatively high-frequency band-reject filter designs. When dealing with low-frequency designs, other filter methods must be utilized, typically using high-Q multilayer RF capacitors.
Low ESL designs
One of the key MLCC stacking technology advantages is its flexibility in electrode / dielectric layers layout. This allows a high customization level to match the technology with specific application field requirements. Low ESL, the high-frequency coupling is increasingly important with the latest generation of processors. The following figure illustrates a possible design configuration to reduce ECL and enable higher frequency operation.
Figure 18. MLCC ceramic capacitors low ESL design options; source: AVX
Lead mount MLCC
Lead mount components are supplied with leads. It can be encapsulated or stacked together by supported J-lead terminations, as in Figure 19.
The purpose of leaded MLCCs is not only to enable the technology for through-hole assembly but, in most cases, to reduce mechanical stress and the risk of cracking at larger case sizes. This is commonly used in high-rel industry or automotive to accommodate larger capacitance values while keeping high vibration robustness.
Leaded MLCCs; source TDK
Stacked MLCCs; source: TDK
Leaded stacked MLCCs; source Exxelia
Figure 19. encapsulated, leaded stuck MLCC ceramic capacitors
Discoidal
In filters and connectors, another chip variant occurs, the concentric one called discoidal, which is often used as a feedthrough capacitor.
Figure 20. Concentric chip (discoidal) feedthrough ceramic capacitors
Figure 21. Discoidal feedthrough ceramic capacitors; source: API Technologies
Failure modes
During the construction report, we have already touched on some of the failure modes that may appear in ceramic capacitors. The most common one in MLCCs is short-circuiting at low voltage in high-impedance circuits. It appears as micro-cracks in the ceramic. Under the influence of moisture and a polarizing voltage, electrolytic material transportation from one electrode to the other easily takes place. We call it “ionic migration.”
We get a short circuit that, to its character, resembles the one that may occur in carbon-contaminated self-healing sites in plastic film capacitors. Similarly, the conductive path is extremely thin and is easily burnt away if the voltage exceeds certain minimum values. Should it, on the other hand, be too high, we get a flash-over in the crack, and this is hardly better.
It is well known that parts manufactured in older technologies had an increasing failure rate that started when the dielectric became thinner than 20…25 μm (» 0.8…1 mil). Even if some manufacturers’ technological progress has improved the quality of thin dielectrics, we still have to be cautious. The failure type is batch-bound and manufacture-dependent, which is connected to the sensitivity to dust and particles in the air.
Dielectric layers thinner than 50 μm (2 mils) require manufacture in clean rooms, i.e., rooms with filtered air and controlled number and size of particles. In other words, knowledge about good manufacturers is a must. Certainly, there are different methods to trace suspicious batches. In the so-called “85/85 test” according to MIL-C-123, the capacitors are exposed to 85% RH at +85°C and a maximum of 1.5 V DC in series with 100 kΩ for at least 240 hrs. However, the efficiency of this test is not one hundred per cent.
Another failure that strikes the common SMD components is bad solderability and silver leaching in more severe soldering processes. To meet the solderability problem, one ought to
- specify and check the packaging method, component age, and solderability in a wetting balance at the relevant soldering temperature.
Hence storage of chips with their exposed terminations should be done in a protected environment. Above all, we should be on our guard for cardboard boxes because they may have a sulfur content which will cover silver alloys with a sulfide layer that destroys the solderability.
The leaching problem can be met with requirements for a barrier layer/nickel barrier. But a general requirement may not be enough. The freedom of pores in the nickel layer and its thickness are important. Besides also here knowledge about the manufacturers is necessary.
There are many pitfalls in the form of poor cleaning from plating bath residues, negligence with the oxidation protection of the nickel layer, etc. Finally, the soldering process might be quite unsuitable for nickel barrier designs. The streaming solder from the wave soldering rapidly conveys heat to the component surfaces and especially to the hard, fast-wetting nickel barrier. Long before the ceramic body has gotten warm, the nickel layer has reacted with its thermal expansion.
In chips larger than 1210, this leads to the risk of cracks in the ceramic inside the nickel barrier, especially if the layer is relatively thick. Therefore, many leading manufacturers make larger sizes without any nickel barrier. But if we from serious manufacturers can find larger sizes with nickel barrier and they are not exposed to wave soldering, but to the slower, more lenient processes like, for example, vapor phase, IR, or hot air, then chip sizes up to 2220 should be possible to use without any risk. Still, larger sizes should have some kind of flexible terminals.
Continue reading at: 3. Ceramic Capacitors Class 1
Source: EPCI
