High CV MLCC DC BIAS and AGEING capacitance loss explained

The past PCNS  2019 Passive Components Networking Symposium [1] introduced MLCC Class II DC BIAS & Ageing Capacitance Loss as the Hot Panel Discussion Topic by five MLCC manufacturers (AVX Corporation, Kemet Electronics, Murata Electronics Europe, Samsung Electro-Mechanic, Wuerth Elektronik) and Continental Automotive as the end automotive user representative at the round table open discussion.

Chicago 2019 Winter Lesson

The Chicago 2019 snowstorms and extreme cold weather heavy loaded the local infrastructure and impacted many “unexpected” aspects towards the people everyday lives. There are some warnings and lessons to learn out of this. For example, the output from regenerative energy sources solar and wind power was close to zero leaving the existing electric power supply network infrastructure in short supply, not sufficient to meet the peak energy demands.

In the electronic sector, the severe weather conditions clearly distinguish between the “good” and “bad” designs of outside environment operating devices. Lips are not moving for a long time at -40C and strong cold wind, so short mobile talk time outside does not hurt so much, nevertheless industrial, safety, infrastructure or automotive systems are required to work reliably, as usual.

We are just entering the era of autonomous devices that will have to process more than 4TB of data per day with its sufficient computing power even at Chicago 2019 winter type of weather. It is clear, for example, that sensors and radar electronics directly faced to the outside environment will have to avoid collisions “without excuse” even in such extreme conditions (that under global warming effect may be seen even more often).

There is a clear need for miniaturization in automotive and other “higher reliability” electronics, but copy and paste approach of some “extreme” designs approaches used in consumer electronics may lead to critical failures there. MLCC class II capacitors with a typically high level of electrical parameter dependency can be one of the components for attention. The passive component industry has to pick its piece of responsibility to provide assistance and help with correct guidelines, provide alternative solutions, clear design rules and referenced “guaranteed” performance specification.

MLCC DC BIAS / AC Voltage & Ageing Capacitance Loss Explained

Ceramic capacitors mostly used in electronics can be split into two main classes of capacitors (see Table 1 and Table 2 below):

1. Class I  – low loss dielectric capacitors with very stable performance but significantly lower capacitance values (no Cap Loss issue and not the main subject of this article)
2. Class II – high dielectric constant but high loss dielectrics

Fig. 1. MLCC class II capacitance loss with time and heat treatment to Curie temperature “reset”; source: Kyocera

MLCC Capacitance with Temperature

Depending on the dielectric type, capacitance changes with temperature – see Fig.2. This is well defined per international standards, and even the dielectric class indicates the temperature stability, including its tolerance field, as shown in Table 1.

Figure 8. MLCC piezo effect illustration, source: Panasonic

MLCC class II capacitors offer a very high level of energy density in miniature sizes that enable a wide range of modern digital devices. On the other hand, the high capacitance density is “compensated” by inferior electrical parameters that may or may not be critical in the specific application area.

There is a multiplication effect of operating conditions that may cause a significant loss of capacitance on MLCC Class II capacitors in real application conditions.

For example – if you select an X5R 0805 10uF 6.3V capacitor as 5V coupling capacitor inthe  operating amplifier, the capacitor may exhibit (depending tothe  manufacturer):

• -60% drop of capacitance due to DC voltage 5V close to 6.3V maximum rated voltage (as per typical data provided by the manufacturer)
• -15% drop of capacitance due to AC voltage being 10mV (as per typical data provided by the manufacturer)
• -10% drop of capacitance due to operating temperature (as per specification sheet)
• -5% drop of capacitance each time decade (as per specification sheet)

The total capacitance value at the actual condition is then defined as multiplications of the capacitance drop factors.

C_actual = C_rated * F _{DCV drop} * F _{ACV drop} * F _{temp drop} * F _{ageing drop}

In example above

C_actual = 10uF * 0.4 * 0.85 * 0.9 * 0.95 = 2.9uF

The actual capacitance value of the 10uF 6.3V MLCC X5R capacitor at the operating condition above is expected to be 2.9 uF.

However, in such operating conditions, the real capacitance value can be as low as 10%, depending on the specific PN design and manufacturer. Designers of electronic devices have to count on such behaviour, and it is always a good idea to check the manufacturer’s datasheets, simulations and detailed specifications. Leading MLCC manufacturers are providing sophisticated online simulation models, where designers can enter their operating conditions, and the software will generate typical plots on the selected part.

How trustful are the manufacturers’ simulation data?

This sub-chapter follows experimental work by I.Novak at col. [2] carried in 2011 on multiple MLCC X5R and X7R vendors.

Figure 7. Compare MLCC 1uF 0603 X5R and X7R 16V vendor data with measured data at reference conditions 500 mVrms AC bias at 100 Hz and room temperature.

Not all of the vendors state the conditions (temperature, AC bias, frequency) for their DC bias data, but our 500 mVrms AC bias data seemed to be more likely to match the vendor conditions than the 10 mVrms data set.

Vendor-B and Vendor-C have very good agreement between measured and vendor-predicted capacitance drop. Data for Vendor-A and Vendor-F show bigger differences, and both predictions underestimate the capacitance loss.

As an important note, it has to be added that manufacturers are continuously improving their software simulation tools and their accuracy. The data presented in Figure 9 are reflecting the situation as present in the year 2011.

Figure 9. Comparison of capacitance % vs bias 1uF 0603 X5R and X7R 16V, at 100 Hz and 500 mV AC. Green triangle markers indicate vendor data; blue line shows measured data. Source: I.Novak; electrical-integrity.com, 2011

Ceramic capacitors are widely used in today’s electronic circuits. Many of them find applications in power conversion and distribution networks. In high-speed data links, they are used as DC-blocking capacitors and occasionally as part of RC terminations. Analogue circuits are also used for timing and DC-blocking applications.

Capacitors in power supplies

Power electronic systems require some minimum capacitance value for IC-safe operational mode. If the voltage drops under the cut-off value, it may result in power supply malfunctions and critical power loss failures. This is very important, especially for safety-critical applications.

MLCC X5R or X7R capacitors are favourite choices for many miniature power designs due to its downsizing, low ESR, low ESL and high ripple current capability. However, the capacitance loss due to the DC Bias Aging impact may significantly lose its capacitance value. The phenomenon depends on various parameters impacting the internal electrical field strength and is thus PN- and manufacturer-specific.

Qualifying a new vendor and using qualified parts at different application conditions without a piece of background knowledge and data can lead to catastrophic system failures. Figure 10 shows a capacitance drop with time example of three manufacturers of the same PN. Blue and black vendors were originally qualified by the end-user, red vendor was added under risk of line stoppage due to the MLCC shortage market situation and resulted in system failures.

Paralleled Capacitors (source: [2])

The application, where the DC and AC bias dependence of MLCCs may need to be taken into account is when we use MLCCs of different capacitance values in parallel (Figure 11).

If the capacitors are assumed to be ideal, as shown on the left of the figure, all that we need to do is, to sum up the different capacitances as they change with DC and AC bias. When their parasitics are also taken into account, the changes of the series and parallel resonances need to be considered as well. The change of capacitances will shift the series and parallel resonances to higher values and Q may also change slightly. If the relative rate of capacitance change is the same for all capacitors, what we get is mainly a shift of the impedance profile to higher frequencies and higher Q at the resonances.

The worst-case occurs, when some of the paralleled capacitance decreases, while some others either don’t or actually might increase, perhaps due to the AC bias conditions.

Such a scenario is illustrated with measured data in Figure 12. Two capacitors were parallel connected in the test fixture: a 1uF 0603-size 16V X7R from one vendor and a 47uF 1206-size 6.3V X5R part from another vendor. The minimum around 1 MHz is from the series resonance frequency of the 47uF part. The minimum around 7 MHz is the series resonance frequency of the 1uF part. The peak around 4 MHz is the anti-resonance between the capacitance of the 1uF part and inductance of the 47uF part. Note that all three resonances move towards higher frequencies, indicating that the capacitances of both parts decrease with increasing DC bias.

Capacitors in LC filters (source: [2])

Probably one of the worst situations is when multiple components joined in the same network, react to DC and AC biases in opposite directions. A typical scenario of this kind is when we use series inductors or ferrite beads for enhanced filtering, followed by shunt capacitors.

If this filter circuit has to handle substantial DC current and the inductive element is not properly sized, its inductance may drop due to the DC current flowing through the part. If at the same time the filtered DC voltage reduces the capacitance of the MLCC part at the output of the filter, we end up with reduced inductance and reduced capacitance, resulting in a significant shift of the filter’s cutoff frequency. This effect was tested with the circuit shown in Figure 13.

The circuit under test was a simple PI filter, composed of two bypass capacitors and a series ferrite bead. The C1 capacitor on the input side of the filter was a 390uF 16V electrolytic type bulk capacitor with little or no DC and AC bias dependence to mimic a low value of input feed impedance. The C2 capacitor on the output was a 47uF 6.3V X5R 1206-size MLCC. The L1 series element was a commercially available ferrite bead, rated for 2A maximum current.

The plot in Figure 14 shows all the measured data traces. The plot on the left has the DC bias voltage and current limited to the reasonable ranges of 0-4V and 0-1A, respectively. The 4V and 1A DC bias limits are 63% and 50% of the rated 6.3V and 2A limits, respectively.

There are two ranges marked on the plot along the two axes: the range of transfer-function magnitude variation at 260 kHz is 50 dB; the range of frequency variation at the -50 dB level is approximately 3.2: 1. The plot on the right shows all traces for the full measured 0-16V bias voltage and 0-1.5A bias current ranges. There are two ranges marked on this plot, too: at 260 kHz the transfer-function magnitude variation is 68 dB; the range of frequency variation at the -50 dB level is approximately 7.2: 1.

The obvious task from designers is to get the worst-case MLCC class II capacitance drop at referenced conditions as the basis for their design considerations. As mentioned in previous chapters, manufacturers are continuously improving the simulation online tools, where typical plots at operating conditions can be simulated to provide information on the capacitor behaviour in the required environment.

The online simulation tools may be sufficient for any kind of consumer electronics operating in the standard environment. Nevertheless, mission-critical system designers can not rely on „typical“ data plots and require a 100% „guaranteed“ point of the capacitance value. Interest in using high CV MLCC in safety automotive, defence or medical systems is increasing under the continuous electronics miniaturisation requirements.

Manufacturers, on the other hand, can guarantee only what they can 100% measure in mass manufacturing.

There are two general ways how to measure Capacitance with DC BIAS: Direct and Indirect capacitance measurement.

Direct capacitance measurement

The direct measurement that is used today in mass manufacturing by most MLCC manufacturers is based on LCR bridge measure meters built into 100% electrical parameter testers. The bridges, contacting systems and el. tester design must ensure the appropriate test accuracy, speed, reliability and lifetime to be able to measure the high quantity of manufactured MLCC capacitors of all kinds and sizes.

Typical LCR bridges used by el.tester manufacturers are a class of HP4263B measure bridges (Fig.15) that are used to measure Capacitance, Impedance, DF or ESR values at frequencies from 100Hz to 1MHz.

While measure parameters of the bridge are satisfying needs for electrical parameters fast and reliable measurement, the DC BIAS conditions are limited to maximum 2V. This complies to standard capacitance reference conditions: Frequency 1kHz or 120Hz AC Voltage: 0.5 or 1.1V AC volt and BIAS of 2V DC.

The LCR bridges can also accept some level of external BIAS, but mostly the value is limited. In the case of the HP4263B bridge, the maximum BIAS level is just 2.5V. More expensive bridges can operate with higher external voltages but are often limited to 50V maximum.

Charging time is another factor that complicates Capacitance with higher DC BIAS measurement. Depending on the capacitance value of the measured part, sometimes constant delay has to be applied before measurement to allow the capacitor to be fully charged. This may be other complication for the adoption of capacitance measurement at el. Tester as there may be only a few (tenth)milliseconds of time slots for the measurement so as not to reduce the tester speed and throughput significantly.

Indirect (transient) capacitance measurement

Capacitor charging and discharging characteristics depend on its capacitance value. Charging current is following the basic equation:

where, I = charging current; dV/dt = voltage increase; C = capacitance

Thus in case of stable voltage increase, dV/dt capacitance value can be calculated based on the measured current value.

The indirect capacitance method during a transient as shown in Figure 16 can be theoretically applicable during measurement of leakage current at rated voltage that is usually part of today’s MLCC capacitors 100% electrical measurements in mass production.

Capacitance (and ESR) values can be also evaluated from discharging characteristics as shown in Figure 17. [3]

Under the constant discharging current, the Capacitance and ESR values can be calculated from equations:

The main challenge of indirect capacitance measurement here is to evaluate its correlation to the Capacitance versus DC BIAS characteristics applicable to a wide range of types and case sizes. Also cost for electrical tester modifications may be of consideration for realistic implementation into mass manufacturing.

• Over the past years, multi-layer ceramic capacitors have undergone significant improvements. The volumetric density has increased severalfold. This unfortunately resulted in a big increase in DC and AC bias sensitivity for many parts. In particular, X5R and X7R parts, which previously showed only modest bias dependence, exhibit significant capacitance drops.
• The increased bias dependence creates additional challenges for users during the design and validation phase and increases design complexity since filters with otherwise identical filtering requirements now may require different component selections if they need to work in different bias environments.
• To help the users, all major vendors today supply at least DC bias information with their MLCC parts and simulation tools under continuous improvement in complexity and accuracy.
• Nevertheless, so far the capacitance versus BIAS data available from manufactures are based on typical characteristics as 100% mass production volume capacitance under the high DC BIAS  measurement present a considerable technical and economical challenge for MLCC manufacturers.

There is a continuous effort to find a common industry approach to the handling MLCC class II DC Bias issues, especially in the automotive industry. Thus, the next proposed step is to involve AEC-Q200 committee members in discussions to recommend a common approach between electronic designers/customers and manufacturers across the industry.

Five manufacturers (AVX Corporation, Kemet Electronics, Murata Electronics Europe, Samsung Electro-Mechanic, Wuerth Elektronik) and Continental Automotive, as the end automotive user representative, discussed this topic during the round table open discussion at PCNS Passive Components Networking Symposium in September 10-13^th 2019 in Bucharest, Romania. The outcome of the panel discussion is summarised in “Open letter to AEC-Q200 committee about MLCC class II Capacitance DC BIAS Ageing issues” and together with this paper, it is submitted for discussion at AEC-Q200 platform.

Future procurement specification, in an ideal case, would define at least one point of the Capacitance versus DC BIAS characteristics that could be “guaranteed” for the selected part.
Procurement specification proposal to be agreed between customer and supplier:

Capacitance loss guaranteed not to exceed XX% (for example -70%)¹ at 100%² of rated voltage, measured at reference conditions: after 12hrs³ post last de-ageing and DC BIAS voltage applied at least for 10hrs⁴ at RT, 1kHz and 1VAC.

The supplier shall also provide typical Capacitance loss with DC-BIAS Ageing charts or link to an online simulation tool. Additionally to the graphs, the supplier shall provide a tolerance band for the graphs which the supplier can guarantee. Such specification would help designers to see some fixed capacitance loss guaranteed working point and evaluate the worst case at the edge operating conditions.

Customer Designer Guidelines:

If you discover that a particular capacitor is unsuitable due to capacitance loss as defined in the specification above, you have the following options:

• You can check if a lower Capacitance DC loss / piezo suppression series is available by a manufacturer (need check with the purchasing team as this can be more expensive part or single source)
• Use a larger capacitance value so that when the capacitance loss is considered, you still have enough capacitance for the required functionality. Note: higher values may have even worse DC bias characteristics due to even higher CV factor. This also may be an issue of distortion in large-signal AC, and likely will just make the problem worse and may not lead to the problem-solving.
• Use a physically larger package size. This would reduce V/mm electrical stress and thus reduces also DC BIAS capacitance loss dependency. So, if you have enough room in your design, moving one step up in case of size, for example from 0402 to 0603, 0603 to 0805 or 1210 will significantly reduce the issue.
• If applicable you can consider using more stable dielectric type such as moving from X5R to X7R, from X7R to X8R dielectric type or tighter tolerance field such as from X7R to X7P types. (multi-sourcing and price increase options to be checked)
• Use a different capacitor type. Sometimes, you won’t be able to escape the DC bias issue or piezo issues at all. In this case, consider looking at a different capacitor type, such as an aluminium hybrid if you have enough board space or a tantalum polymer capacitor that may provide low profile, high CV and stable option.

• The level of defined maximum capacitance loss may be a part number specific, the actual value or some more detail guideline, if possible, to introduce some general rules to be discussed with manufacturers
• The cap loss reference DC BIAS is suggested to 100% of rated voltage, but it can be changed upon discussion with manufacturers.
• 12 or 24hrs measurement after last heat/dealing is a standard time used also in MIL standards to define the state of the dielectric after the last “reset”.
• 10hours of DC applied as reference selected with respect to decades behaviour references that is used by MLCC manufacturers… what is happening in first, second, the third decade …etc. 1hour may not be sufficient in some cases to see all slow polarization to happen and need to add some safety, thus 10hours (or more) is set as the reference point.