Ceramic Class 2 capacitors can be divided into two main groups, one with a moderate temperature dependence for the class – ΔC ≤ ±15% within the temperature range – and the other with such changes that only a fraction of the capacitance remains at the temperature limits. The first group is represented in our tables and diagrams by the ceramic type denominated X7R or 2C1, the latter by Z5U or 2F4.
This article is the last part of a complete installment on the construction, manufacture, application and characteristics of ceramic capacitors, divided into 4 sections:
- Introduction to Ceramic Capacitors
- Construction & Manufacturing Process
- Ceramic Capacitors Class 1
- Ceramic Capacitors Class 2
Introduction to class 2 ceramic capacitors
Class 2 capacitors are characterized by high dielectric constants, often designated with a K followed by the εr. Hence K2000 means εr ≈ 2000. The temperature dependence of the capacitance is large. Therefore EIA characterizes the ceramic with three characters that state the lower and the upper limit of the temperature range and last the capacitance change within the range.
Table 4. Ceramic capacitors EIA codes for temperature limits and capacitance changes, ΔC.
Example: X7R means with EIA designations the temperature range -55/+125 °C where the capacitance change maximum ±15%, provided the DC voltage is zero. The EIA code doesn’t consider that the Class 2 ceramic reacts with capacitance reduction to DC voltages.
On the other hand, certain other standards do. Here are some examples.
Table 5. Comparisons between ceramic capacitors classes. ΔC versus temperature and VDC.
Table 5. contains two main groups of Class 2 ceramics:
• K900⋅⋅⋅K2200; ΔC approximately ±20% within the temperature range.
• K4000⋅⋅⋅K12 000; very large ΔCs at the temperature limits.
Within these groups, there are many more materials, for example, the recent material Y5V, but in our diagrams and table information, we will mostly confine ourselves to X7R/2C1 and Z5U/2F4. By specification, Z5U is situated within a more limited temperature range than 2F4, but this has to do only with the specified ΔC, not with its capability to stand up to lower temperatures.
If we accept the capacitance changes caused by cold the ceramic will stand at -55°C. In the diagram section, we shall look closer at the temperature dependence of the capacitance. The upper-temperature limit, however, should not be exceeded. The capacitance tolerances for X7R usually are ±5, ±10, or ±20%. Usual Z5U tolerances are ±10, ±20 or -20/+80%. See also the figure below.
MLCC ceramic capacitor dielectric capacitance changes with temperature; source: Samsung Electro-Mechanics
The dielectric absorption is high:
• X7R/2C1 ≈ 2.5⋅⋅⋅4.5%;
• Z5U/2F4 ≈ 4.5⋅⋅⋅8.5%.
Measurement conditions
Table 6. class 2 ceramic capacitors reference measurement conditions.
The measuring voltage is specified and limited depending on the capacitance, which changes with the applied alternating voltage. See examples in Figures 34 to 38.
Figure 34. Examples of class 2. ceramic capacitors ΔC versus measuring voltage for X7R/2C1 with different rated voltages
Figure 35. Examples of class 2. are ceramic capacitors ΔC versus electric tension for Z5U/2F4 with different rated and reference voltages.
The Curie temperature
Ceramic capacitors have a crystalline structure and dipoles that give the materials their unique dielectric constants εr. But the ceramic loses its dielectric properties above a certain brittle transition temperature, the so-called Curie temperature. The Curie temperature for Class 2 ceramics is usually between 125⋅⋅⋅and 150 °C. The influences don’t occur at any exact switch temperature but make themselves gradually discernible in the vicinity of the Curie temperature. Thus, we should talk about the Curie range.
C 2.11.4 The dependence of capacitance on an applied voltage
Dielectric absorption (DA) and Ferroelectricity
The different types of Class 2 ceramics are based on barium titanates. Their crystalline structure is constituted by dipoles that present a dielectric hysteresis at the polarizing. With patterns from the hysteresis curve of magnetic materials, they are called ferroelectric.
Figure 36. shows the capacitor charges versus the applied voltage.
When the voltage increases from zero to a limit value and then decreases, the charging curve follows another branch that at the voltage V = 0 leaves a residual charge + ΔQ. An alternating voltage of the same magnitude will force the charging curve along the outlines of the large hysteresis loop in the figure.
If the alternating voltage is small and the DC voltage = 0, the hysteresis loop will follow the small oval in the center of the figure. Small voltage changes correspond to large charge changes, i.e., high capacitance. But if we superimpose a small alternating voltage on a considerable DC voltage, we see how ΔV1 corresponds to fainter charge changes ΔQ1. The capacitance has dropped.
Figure 36. Capacitor dielectric material with ferroelectric hysteresis.
Figure 36. The ferroelectric material locks a residual charge ΔQ on the electrode surface when the voltage over the capacitor recedes to zero (outer circuit short-circuited). In other words, it’s a question of dielectric absorption (DA). But there is a difference, too.
The ferroelectric curve swings to the V axis while the general DA curve looks like a magnified picture of the center oval. In both cases, the bound residual charge ΔQ is time-dependent. If the outer circuit is short-circuited (V = 0), successively, charges on the electrode surfaces are set free while ΔQ decreases.
The ferroelectric energy absorption is polarity-dependent. Thus a complete re-polarizing will require more energy than the initial polarizing. But in, for example, D/A converters, the pulse time may not be sufficient for a satisfactory re-polarizing.
The considerable dielectric absorption in Class 2 ceramics makes them directly inappropriate for precision integrators like D/A converters, especially if there are positive and negative pulses. The crystalline structure of ferroelectric materials is maintained up to the Curie temperature.
A specific group of materials is anti-ferroelectric dielectrics, as we discussed in the introduction and Figure 3.
Piezo-electricity
If we expose a Class 2 ceramic material to electric field strength, it will cause faint movements in the ceramic. Inversely a mechanical pressure will create electric charges in the capacitor. The phenomenon is called piezoelectricity. BX ceramics (K900⋅⋅⋅⋅⋅⋅⋅⋅⋅K1800) exposed to chock/vibration produced in an experiment output voltages up to 40 mV3.
If we connect an X7R capacitor to an oscilloscope and bang a hammer on the component, we sometimes get high voltage spikes, sometimes not. It depends not only on how the blow hits but also varies from one sample to another. The output voltage is both manufacture and batch-dependent.
DC voltage dependence
We showed just by reasoning around the ferroelectric curve how the capacitance decreased with an increasing DC voltage. Figure 37 shows how the DC voltage influences the capacitance. Notice how specification requirements of voltage dependence affect equivalent materials in other respects.
For X7R, no requirements are called for – the dependence will be great –for 2C1, the dependence is maximized to –30%. Within the material classes, the voltage dependence increases with the rated voltage. The dielectric thickness, namely, doesn’t grow in proportion to the rated voltage. Thus, the electric field strength increases with increasing rated voltages, leading to a somewhat enhanced voltage dependence.
AC voltage dependence
Alternating voltages create a reverse effect, unlike DC voltages, on capacitance.
Let us emphasize Figure 38. represent one example. Great variations may occur. In any case, norms’ significance for capacitance measurements is obvious. At IR measurements and voltage tests, MIL and IEC/CECC specify a charge and discharge limitation of a maximum of 50 mA.
Commentary: The limitations are questionable. Some manufacturers have chosen to delete these requirements in their catalog sheets. Some even specify voltage rise times of 1000V/μs, which for capacitances above 1 nF means surge currents ≥ 1A!
If your application requires considerable charge/discharge currents, please check with the manufacturer – or test for yourself – what the capacitor can stand and restrict the application to single pulses. Class 2 ceramics don’t stand an intense periodic pulse load.
Aging
Class 2 ceramics lose capacitance with time. The decrease is called aging. It conforms to a logarithmic law and decreases with a certain percentage per decade.
In the diagram the capacitance of the Z5U ceramic decreases by approximately 6% per time decade and of the X7R ceramic by approximately 1.3%.
Typical aging constants usually are
• BX/X7R/2C1 1⋅⋅⋅2%
• Z5U/2F4 3⋅⋅⋅6%.
The aging constant k, expressed in percent per decade, follows the general formula.
The capacitance decrease is defined as starting 1 hour after cooling. To avoid disputes about delivered values, relevant norms state that the value shall be guaranteed at the 1000 hrs. With starting point from the formula, C2-2, the 1000 hrs value is then calculated as
If a temporary DC voltage in the magnitude of VR is applied, there will be a lingering effect in the form of a capacitance decrease more or less as if the component had been aged for 1⋅⋅⋅1½ time decades (Figure 40.).
The figure also shows how the capacitance value increases to some extent when the DC voltage – here approximately VR – is removed.
The increase can amount to approximately
• +2.5% for C21 ceramics
• +5% for X7R and Z5U ceramics.
The aging starts by definition 1 hour after cooling. Now, if we heat a capacitor above the Curie point and let it cool, the crystal structures orientate themselves in the same way as after the manufacture, and the capacitance resumes its initial value before it, again, starts subsiding by the aging curve. One talks of “de-aging.”
Mind that every soldering of chip ceramics results in damage. De-aging effects may be evoked already in the lower part of the Curie range if the distance to the Curie point is compensated by a corresponding increase in time.
DC BIAS Ageing Effect
Ceramic class II capacitance loss with DC, AC, Temperature, and life might be multiplicated. To ensure the capacitor meets all requirements, attention must be paid to evaluating all final electronic hardware operating conditions. This is important, especially in mission-critical and safety applications.
Temperature dependence
Capacitance versus temperature and voltage
Figure 37. Typical curve range for ΔC versus DC voltage in different ceramic capacitor dielectric material classes
Figure 38. Examples of ΔC versus AC voltage in percent of the rated voltage VR of class 2. ceramic capacitors.
Figure 39. Example of class 2. ceramic capacitors dielectrics aging diagram for X7R and Z5U ceramics.
Figure 40. Aging effect from a momentary DC voltage in the magnitude of VR on class 2. ceramic capacitor dielectric
Figure 41. Typical curve range for class 2. ceramic capacitors capacitance versus temperature in X7R/2C1, with and without rated voltage applied.
Figure 42. Typical curve range for class 2. ceramic capacitors capacitance versus temperature in Z5U/2F4, with and without rated voltage applied.
Tan δ versus temperature
Figure 43. Typical curve ranges and average curves for class 2. ceramic capacitors dielectric Tan δ versus temperature in X7R/2C1 and Z5U/2F4
IR versus temperature
Figure 44. Typical examples of the IR versus temperature in class 2 ceramic capacitors chips.
The insulation resistance in Class 2 ceramic capacitors decreases with, on average, one power from room temperature to +125°C typically.
Frequency dependencies
Capacitance and Tan δ versus frequency
Figure 45. Typical curve ranges for capacitance and Tan δ versus frequency in X7R and 2C1 class 2. ceramic capacitors.
Figure 46. Typical curve ranges and average lines for capacitance and Tan δ versus frequency in Z5U / 2F4 class 2. ceramic capacitors dielectrics.
Impedance and ESR versus frequency
Figure 47. Examples of impedance and ESR versus frequency in X7R and 2C1 class 2. ceramic capacitors dielectrics
Figure 48. Examples of the frequency dependence of impedance and ESR in 2F4/Z5U class 2. ceramic capacitors dielectrics.
Figure 49. Other examples of the frequency dependence for impedance and ESR on class 2. are ceramic capacitors dielectrics.
Table 7. CERAMICS CLASS 2 / X7R-2C1 / Z5U-2F4 CHARACTERISTICS
Source: EPCI
