Capacitors Class 1 are manufactured using low-loss linear paraelectric ceramic dielectric materials with low-temperature coefficients between +100 and –1500 ppm/°C. NP0 or COG (0 ± 30 ppm/°C) types dominate all remaining Class 1 variants.
To the Class 1 ceramics, we also count porcelain that is found in specific HF chips above all.
This article is the third part of a complete installment on the construction, manufacture, application and characteristics of ceramic capacitors, divided into 4 sections:
- Introduction to Ceramic Capacitors
- Construction & Manufacturing Process
- Ceramic Capacitors Class 1
- Ceramic Capacitors Class 2
General comments to class 1 capacitors
The type is characterized by small losses, high IR, high stability, linear and moderate TCs between +100 and – 1500 ppm/°C, and an εr between 5 and 450. The tolerances range down to ±1%. Capacitances lower than 10 pF are challenging to produce to a percentage accuracy. The tolerances are instead stated in absolute values: ±0.1pF, ±0.25pF, ±0.5pF, and ±1pF.
At construction and failure analysis, you may sometimes find a pit in the ceramic of Class 1 capacitors. It may extend through all layers and is filled with some inert compound, often glaze. It is a so-called trim pit where part of the electrode surface is blasted away to match the capacitance value towards more acceptable tolerances, for example, 1 or 2%.
The ceramic mass shrinks enormously during the sintering – approximately 15% –and this may cause the capacitance distribution to get so skewed that it will be necessary to adjust it by trimming. The trim pits are harmless, provided the filling compound doesn’t contain blisters at the edge of adjacent layers.
The small losses in Class 1 ceramics do not correspond to a similarly low dielectric absorption. On the contrary, it is relatively high, approximately 0.5…1%.
The dielectric consists either of one layer – as a tube or in a plane shape, SLC from Single Layer Ceramics, or by several layers in stacked form, MLC from Multi-Layer Ceramics. In MLCs, the capacitance range is determined by the number of layers. At a minimum, it consists of one layer; at a maximum, it is limited by the manufacturing technique and for economic reasons. The noble metal AgPd paste of the electrodes is expensive; mostly, BME is a cheaper variant.
The temperature coefficient often is denoted by N(negative) or P(positive), followed by the value in ppm/°C. Here are some examples where we within brackets also mention the corresponding EIA designation:
- P100 = +100±30ppm/°C; (EIA = M7G)
- NP0 = 0±30ppm/°C; (EIA = COG)
- N150 = -150±30ppm/°C; (EIA=P2G)
- N1500= -1500±250ppm/°C; (EIA=P3K).
US MIL specifications have other designations.
In diagrams and tables, we confine ourselves to the predominant NP0/COG ceramic.
HF chips
When the frequency rises to some hundred MHz, conventional ceramics in MLC design start reacting with high and exponentially increasing losses. We come to a step on the way by modifying the ceramic. By passing to porcelain (εr = 12…15), which we include under the concept ceramics Class 1, the losses decrease sharply. Another way to reduce the HF losses is by passing to a single-layer design, SLC, and introducing thin film electrodes in gold (Au), copper (Cu), or aluminium (Al). As a dielectric silicon dioxide (εr = 4.4) or silicon nitride εr = 7.5) is used.
Sometimes a changeover to a mica capacitor chip can reduce the losses.
The HF capacitors’ losses are expressed sooner in the quality factor Q (=1/tan δ) than in tan δ.
Measurement conditions
At IR and voltage strength tests, sometimes in MIL and IEC/CECC, a maximum charge and discharge limitation of 50 mA is specified. Comments: These limitations are probably based on older manufacturing technologies. Some manufacturers nowadays have chosen to delete these requirements in their catalogue sheets. Corresponding voltage rise times will be for capacitances above 1 nF to be unrealistically low. According to performed tests, such capacitors manage at least 100 to 1000 times higher inrush currents, even at repetition frequencies in the kHz range.
Diagrams
We shall present several diagrams describing the different temperature and frequency characteristics as usual.
Temperature dependencies
Table 2. Measurement conditions Class 1 ceramics
Capacitance and Tan δ versus temperature
Figure 22. Class I ceramic capacitors capacitance and Tan δ versus temperature. Typical curve ranges for NP0/COG.
IR versus temperature
Figure 23. Class I ceramic capacitors’ typical curve range for IR versus temperature
Comments to Figure 23 about RC product and IR.
When we convert the RC product to insulation resistance (IR) expressed in MΩ and go down in capacitance, the IR increases correspondingly. Specifications usually set limits to the IR increase at 10 nF. According to the typical curve in the figure, RC is approximately 4000 s at 25°C, which gives an IR = 4000/10(nF) = 400 GΩ. Larger values can not be expected for capacitances lower than 10 nF.
Frequency dependencies
Capacitance and Tan δ versus frequency
Figure 24. Class 1. ceramic capacitors Capacitance and Tan δ versus frequency. Typical curve range for NP0/COG.
Q versus frequency
Figure 25. Information about Q value versus frequency for porcelain and ceramic class 1 ceramic capacitor chips.
Notice how the Q value increases with decreasing capacitance and chip size. Figures 25. and 27. show examples of the same phenomenon.
Figure 26. Example of class 1. ceramic capacitors Q value versus frequency.
Figure 27. Another example of class 1. ceramic capacitors Q value versus frequency and chip size.
ESR for the same chip as in Figure 27. is shown in Figure 28. Other examples of the frequency dependence of ESR are found in Figures 29 to 31.
ESR versus frequency
Figure 28. Examples of class 1. are ceramic capacitors ESR versus frequency.
Figure 29. Another example of the class 1. ceramic capacitor ESR for 1 and 10 pF.
Figure 30. Class 1. ceramic capacitors ESR examples for 10 pF and 10 nF.
Figure 31. Examples of class 1. are ceramic capacitors ESR and impedance versus frequency in a chip and a lead mounted 1 nF capacitor.
Resonance frequency versus capacitance
Examples of series resonance frequency versus capacitance for two sizes of HF chips in MLC design are shown below.
Figure 32. Examples of class 1. ceramic capacitors series resonance frequencies for HF chips in MLCC technique.
Figure 33. Example of class 1. ceramic capacitors resonance frequency in an SLCC chip.
As a comparison to the MLC example above, Figure 33. shows how a SLC chip in approximately the same size as 0603 may behave.
Table 3. CERAMICS CLASS 1 / NP0 / COG CHARACTERISTICS
