A supercapacitor balancing system is required to avoid overloading individual supercapacitor cells in a series connection. Würth Elektronik’s technical article by René Kalbitz explains some theoretical background of supercapacitor balancing methods and verifies their effectiveness in practical measurement and comparison. They are published under Würth Elektronik’s permission.

Supercapacitors (SC) usually operate at low voltages of around 2.7 V. To reach higher operating voltages, it is necessary to build a cascade of SC cells. [1] [2] Due to production or ageing-related variations in capacitance and insulation resistance, the voltage drop over individual capacitors may exceed the rated voltage limit. Thus, a balancing system is required to avoid accelerated aging of the capacitor cell. [3] [4].

In the following posts, we want to explain the principle effect of unequal voltage division in such cascades. To improve the under-standability, we consider a series stack of two capacitors (note: any system may be reduced to an equivalent circuit of two capacitors.). This note reviews the theoretical background, provides some measurements, and discusses practical examples. The goal is to provide an overview of possible balancing strategies and an understanding of the explained concepts. The developer can choose and adapt any system to meet specific requirements.

1. Balancing Theoretical Background

This part delves into the principles of balancing currents and times in capacitors, particularly when considering their tolerance ranges. It provides equations to estimate the necessary current to equalize voltage differences between capacitors in series. For instance, with a nominal capacitance (Cr) of 10F and a tolerance range of -10% to +30%, the actual capacitances could be 9F and 13F. The article emphasizes the importance of calculating the appropriate balancing current and time to ensure efficient capacitor performance.

2. Supercapacitors Balancing Strategies

Supercapacitors connected in series require balancing strategies to address voltage imbalances caused by variations in capacitance and insulation resistance. These strategies are categorized into passive methods, such as resistors and Zener diodes, which are simple and cost-effective but may result in slower balancing and higher power dissipation, and active methods, like op-amps and MOSFETs, which provide faster and more efficient balancing but are more complex and expensive. The choice of balancing method depends on the specific application’s requirements for speed, power efficiency, and cost.

3. Measurements

This section examines various methods for measuring and balancing voltages in supercapacitors, particularly when connected in series. It discusses passive balancing techniques, such as using resistors and Zener diodes, highlighting their simplicity and cost-effectiveness, though noting potential drawbacks like increased power dissipation and slower balancing times. The article also explores active balancing methods, including the use of operational amplifiers and DC-DC converters, which offer improved balancing efficiency and reduced energy losses but come with added complexity and cost. Through practical measurements and evaluations, the article provides insights into the effectiveness of these balancing strategies, aiding in the selection of appropriate methods for specific applications.

4. Summary – What is the Best Supercapacitor Balancing Method?

This part evaluates various supercapacitor balancing methods, analyzing their balancing speed, power dissipation, and cost-effectiveness. Passive methods, such as resistor balancing, are noted for their simplicity and low cost but offer slower balancing speeds. Active methods, including those utilizing operational amplifiers (OP-AMPs) and DC-DC converters, provide faster balancing but may involve higher power dissipation and increased complexity. The article emphasizes that selecting the optimal balancing strategy depends on specific application requirements, considering factors like availability, lifetime, and design-in time.