Impedance peaks caused by parallel L-C resonances in the power distribution network (PDN) are potential sources of power rail ripple and increased EMI. Bulk capacitors must be selected to ensure power supply stability while high-frequency decoupling must provide the required bandwidth at the Load.
Simple SPICE simulations fail to account for PCB parasitics and often result in the wrong selection of decoupling capacitors. Utilizing EM models of the PDN and combining them with power supply state-space models and the spectral requirements of the load results in good agreement with measurements.
Optimizing this PDN ecosystem shows that designing for flat impedance is the best way to achieve the lowest noise on the power rail with the minimum number of capacitors.
Main topics covered in the video
- Introduction to power integrity anddecoupling capacitors
- Understanding decoupling capacitor selection
- Optimizing decoupling for target impedance
- Impact of parasitic elements on decoupling performance
- Practical demonstrations and measurement comparisons
- Paralleling decoupling capacitors and their effects
- PCB design considerations for power integrity
- Using simulation tools for optimization
- Final recommendations for power integrity design
- Resources and next steps
Source: Picotest
