- Posted by Emilio Cano García
- On November 6, 2020
Data Device Corporation has compiled a list of frequently asked questions related to its EEPROM family.
Below, you can see the list categorized into three sections:
The DDC family of EEPROMs are in-circuit programmable. For applications where the device must be programmed prior to insertion, there are a number of programmers that can be used to program DDC’s EEPROM devices. Although DDC does not recommend a specific programmer, the user should choose a programmer based on the performance and flexibility required. DDC’s family of EEPROMs utilize the Hitachi HCN58C1001 EEPROM die. The 1 Megabit and 4 Megabit devices can be programmed with the HN58C1001 Hitachi programming algorithm available from most programmer manufacturers.
The 1 Megabit EEPROM devices, in the DIP package, can be directly programmed by any programmer that has Hitachi programming algorithm support. For the flat package devices, a DIP to Flatpack adaptor can be purchased from the programmer manufacturer or constructed by the user.
The 4 Megabit EEPROM devices, 79C0408, contain four 1 megabit EEPROM die, with the pins all paralleled except for the four chip enable control inputs. A special adaptor board, similar to Figure 1., needs to be constructed with a 4 position switch, which the four chip enables are wired to. Using the chip select switch, the device is programmed one EEPROM die at a time.
The 8 megabit devices, 79C0832, 32 bit I/O configuration, standard programmers can not be used. If a device has to be programmed prior to being installed on the PCB, a custom programmer will have to be designed and fabricated.
For DDC family of EEPROMs, the erased state is logic level “1”. Devices are shipped to the customer in the erased state; that is, all bits are shipped with a logic level “1”.
The typical time to program a byte or a page of data is less than the maximum time specified in the datasheet. The user can either wait the maximum time specified to perform the next operation or the RDY/BUSY pin or the data polling bit can be monitored to determine when the program cycle has been completed. When a program operation is being performed, the RDY/BUSY pin will be pulled low. When the operation is finished, this pin will be tri-stated. An external pull-up resistor can be used to pull the pin to a HIGH state. Since the RDY/BUSY pin is an open-drain output, several RDY/BUSY pins can be tied together in parallel with a single pull-up resistor to Vcc.
In designs where the use of the RDY/BUSY pin is not practical, the user can use the data polling feature to determine the end of a program cycle. Data polling is available on the I/07 pin. When the data is read from the last address programmed during a programming cycle, the I/07 bit will be the complement of the bit that was to be programmed. After the programming cycle is complete, the I/O7 bit will have the correct data.
For a 5V device, the maximum time it takes to program a byte or a page is 10ms, twc. For a 3.3V device, the maximum time to program a byte or page is 15ms.
An erase operation is not required for DDC family of EEPROMs. After the byte load cycle is complete, the bytes to be written are first erased and the new data is written.
When data is loaded into memory the address is latched on the falling edge of /CE or /WE whichever comes last. Data is latched into the device on the rising edge of /CE or /WE whichever comes first. For writing data to the device, the only requirement is that both/ CE and /WE go LOW for the specified write pulse width.
DDC’s EEPROM devices feature software data protection, which is implemented using a JEDEC standard algorithm. When EEPROM devices are shipped from DDC, software data protection is disabled allowing users to program the devices with commercial EEPROM programmers that do not support this feature. With software, protection enabled unintentional writes to the EEPROM are avoided.
With software data protection (SDP) enabled, there are two methods of writing to the EEPROM. Each byte or page written to memory must be preceded by the 3-byte protection sequence or software data protection must be disabled. The preferred method for writing to the memory is to load the three-byte software protection algorithm, which temporarily unlocks software protection, load a byte or page of data and wait 10ms for the write cycle to complete. Once the write cycle completes the software protection will then be enabled. The three-byte software protection algorithm is not written to memory, only the data that follows. Once enabled, software data protection will not be reset during power down of the device.
To disable software data protection a six-byte algorithm is loaded followed by a byte, up to the page, of data and the tWC write cycle is allowed to complete. Once software protection is disabled the device can be written to, and the three byte-locking algorithm can be loaded to enable software protection.
DDC does not recommend using the six-byte disable code to unlock the protection. By using only the three-byte sequence rather than the six-byte sequence, the user is assured that the Software Data Protection is always enabled and that inadvertent writes will not corrupt the data in his memory.
To determine if software protection is enabled, a byte of data is written to the device without the three-byte protection algorithm. A read is then performed on the address that has just been written to. If the data does not change in that location then software protection is enabled. If the data does change then software protection is disabled.
The datasheet specifies specific timing and signal requirements for the /RESet input to ensure data protection during power up and power down sequencing. This timing is difficult to implement during unexpected power down occurrences. What is the minimum requirement to ensure data integrity during an unexpected power down sequence?
The proper use of the /RESet input must be used to fully ensure data integrity. During an unexpected power-down sequence, the /RESet input must be less than or equal to 0.5V. If the /RESet input is held at the proper level during power down the data will be protected even if the input signals /CE and /WE are not properly controlled.
DDC guarantees 10,000 erase/write cycles in the Page Mode. When the 1 Meg EEPROM is in the page mode it will latch a page (128 Bytes) of data and write them in a single write cycle. This operation counts as one erase/write cycle for each of the 128 bytes in the page.
A page is also divided into 16 subpages each consisting of 8 bytes. The sub-page is the minimum unit of programming.
In the byte-programming mode, input data is one byte, however, 8 bytes of data are written internally because of the minimum programming size. The eight bytes written is the one byte of input data and the 7 bytes of the same data previously written to the memory cell. If data is programmed into address N for 10,000 times, then addresses N+1 to N+7 are also programmed 10,000 times.
Because of the 8-byte sub-page architecture, that is the minimum programming unit, it is only practical to erase/write one eighth as many times as the page mode guarantee.
When a portion of a page is written, only the subpages that are updated will be erased and written. Example 1) If the first 64 bytes of a page is written to, only the 64 bytes will have an erase/write operation. Example 2) If the first byte of each of the 16 subpages is updated then the entire 128 pages will have an erase/write operation, due to the minimum programming unit.
The ten-year data retention specification assumes the device in an un-powered state over the operational temperature range.
The standby current is measured with the /CE input HIGH. The standby current specifications shown in the data sheets reflect the different standby currents for CMOS inputs and for TTL inputs.
Operational current is the current measured during the read cycle. Operational current is dependent on the data access rate. The operational current specifications shown in the data sheets specify the cycle time of the device for each Icc listed. At lower address frequencies, the operational current measured will be less than those listed in the datasheet.
The byte load cycle time spec, tblc, is 30us. Once a byte of data is loaded, another byte of data must be loaded within 30us to assure the internal latches will accept the data. If the next byte of data is not loaded within 30us, the part will begin the programming cycle and any additional attempts to load data will be ignored.
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