Validation ASIC Space Applications
- Posted by doEEEt Media Group
- On February 19, 2021
- 0
Introduction
Traditionally ASICs Space applications (and FPGAs) used in space were manufactured using Rad-Hard technologies and designed with special libraries.
AS CMOS Technologies became denser (beyond the 180 nm node) it was realized that it was no longer affordable to change the semiconductor technology and that hardening had to be assured by other means.
With DSM, access to technology has become even harder for space users.
As a result, today, in many cases (especially for smaller users) each box in the design flow below is assured by a different entity.
Alter Technology has implemented an independent global solution which takes over right after foundry.
Validation ASIC Space Applications Video Presentation.
Speaker:
Agustín Coello Vera from Alter Technology, during the presentation at MEWS , Tsukuba International Congress Center in Japan.
What about space requirements?
For space most of what it has been learned by the designers, coming from other sectors, does not apply.
In the space, the radiation, thermal and mechanical requirements are quite different to anything known to ASIC designers.
Highly skilled designer will fail out in the SPACE unless the entire supply chain is properly addressed.
A team of experts that brings you the latest and most important news about the EEE Part and Space market.
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