- Posted by doEEEt Media Group
- On February 17, 2020
Accelerators are the accepted method to validate a device to flight. In vivo testing is a complex and expensive task that is needed to get information about how failures can propagate to primary outputs and monitor that the response of a design is correct.
There is a strong dependence between the design and test stimuli and the number of errors collected in a test of a complex circuit.
Fault Injection is an inexpensive technique that during design time, refine the design for the test fixture, improve the quality of stimuli, in order to maximize the error rate, and test the design observability.
The talk will present a practical tool useful for the design behavior prediction, in order to help to develop a good mitigation scheme and to develop a good test plan. This tool is also suitable to develop test plan for FPGAs.
Emulation and failure injection, a complement to Radiation Test
Principles of Fault Injection
Emulate the particle hitting using a controlled process in an FPGA as design support device.
The injected fault is a model of the physical effect under study.
- After an injection the result is recorded into a Fault Dictionary.
- The procedure is repeated a significant number of RUNS. This is called CAMPAIGN.
REMARK: This mode of Fault Injection is done over the USER REGISTERS:
- SEU -> Simple bit flip
- MBU -> Several simultaneous bit flips paired by the layout
- SET -> Several simultaneous bit flips capturing the transient pulse propagated through the logic cones and captured by the registers.
Faults on configuration memory
- Faults are permanent modification of the circuit
- Faults (in principle) do not propagate to other configuration memory cells
- Faults are related or unrelated to the configured circuit.
- Faults related:
• Produce an electrical influence
• Critical -> Can be compensated by
• Propagates to other configuration points
Xilinx produces part of this information in the “essential bits” file